Memory systems typically have a controller that manages access to storage. Herein, this controller will be referred to as a “memory controller.” The storage could have flash memory cells (e.g., NAND, NOR), resistive random access memory (ReRAM or RRAM), phase change memory (e.g., PCM), etc. The memory controller receives memory access commands (e.g., read write) from a host. The memory access commands typically indicate a starting logical address and a data length. The starting logical address could be a logical block address (LBA). The data length could be specified in a data unit, such as a block. The size of a block can vary from one implementation to the next. The memory controller translates the logical addresses to physical addresses in the storage. As one example, a flash memory device has a Flash Transfer Layer (FTL) or Media Management Layer (MML) that performs a logical address to physical address translation.
In some memory systems, the memory controller does not queue memory access commands from the host. Rather, the memory system receives a memory access command from the host, executes the memory access command, and sends a response to the host. Then, the host sends another command to be executed. For example, the memory system receives a read command, as well as logical address and data length, from the host. The memory system senses the data from the storage and provides that data to the host. Then, the host sends another read or write command.
In other memory systems, the memory controller maintains a command queue of memory access commands from a host. It is common to refer to the memory access requests from the host as “tasks.” Hence, this command queue may be referred to herein to as either a “task command queue” or a “command queue.” A task typically includes multiple commands from the host. For example, the host might send one command to indicate a read is requested, another command to provide the logical address and data length, and still another command to execute the read.
The memory controller indicates when a task on its command queue is ready to be executed. In the context of a read command “ready to execute” means that the memory controller will provide the data to the host within a specified time. In the context of a write command “ready to execute” means that the memory controller will program the data to storage within a specified time. The memory controller may maintain a task status register that indicates whether each task on the task queue is ready to be executed or not. To cause the memory controller to execute a task, the host first checks the status by, for example, sending a command to the memory controller to check the task status register. After the memory controller indicates a task is ready to execute, the host sends an execution command to the memory controller to instruct the memory controller to execute the task. Typically, the memory controller has a set amount of time to complete the task after the host sends an execution command. For example, the memory controller might have 100 milliseconds (ms) to provide the data for read command and 250 ms to program the data for a write command.